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Cologne Chip AG USB Drivers » Scan Computer for Cologne Chip AG Driver Updates Intelligent ISDN USB WAN-Miniport + Capi 2.0 (For serial number 46000202 or high. Cologne Chip AG IP Catalog About Cologne Chip AG. Under the name 'C3IP' (Cologne Chip IP Cores), Cologne Chip offers innovative ASIC IP Cores. The product line consits of PLLs and CODECs (DAC/ADC) based on a completely new design technology: DIGICC Technology.

GateMate^TM FPGA

Suitable from university projects up to high volume applications

The GateMate^TM FPGA family of Cologne Chip AG addresses all application requirements of small to medium size FPGAs. Very low power and speed applications are feasible. Logic capacity, power consumption, package size and PCB compatibility are best in class. GateMate^TM FPGAs combine these features with lowest cost in industry making the devices well suited from University projects to high volume applications. Because of the outstanding Circuit size/Cost ratio, even new applications now can use the benefits of FPGAs.
All this is based on a novel FPGA architecture combining a special Central Programmable Element (CPE) with a smart routing engine. Furthermore, arbitrary size Multipliers are usable. Memory aware applications can use block RAMs with bit widths of 1 to 80 bits. Even bit-wise enable is possible.

General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volt. GPIOs can be configured as single-ended or LVDS differential type. Furthermore a high speed SerDes interface is available.
GateMate^TM FPGAs are supported by EasyConvert^TM, that enables the transfer of existing FPGA designs without new synthesis. Worldclass P&R-software maps and implements the design into GateMate^TM FPGA.
A Static Timing Analysis (STA) is also performed and gives evidence about critical pathes and the overall performance of a design. The design can be easily simulated using Verilog netlist and SDF timing extraction.
The devices are manufactured using Globalfoundries^TM 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high taxation.

GateMate^TM FPGA Overview

The CCGM1A1 FPGA is the smallest-dimensioned component of the GateMate^TM Series. With its 20,480 logic elements, it is ideally suited for lowest-power applications.

GateMate^TM FPGA Features

Novel CPE Architecture

• 20,480 programmable elements for combinatorial and sequential logic
• 40,960 Latches / Flip-Fops within programmable elements
• CPE consists of LUT tree with 8 inputs
• Each CPE configurable as 2-bit full-adder or 2x2 multiplier

Low Power Consumption

• Globalfoundries^TM 28 nm SLP (Super Low Power) process
• 3 operation modes: low power, economy, speed
• No excessive start-up currents
• Only two supply voltages needed, can be applied in any order

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Features

• 4 programmable PLLs
• Fast configuration with quad SPI interface up to 100 MHz
• Multi-Chip configuration
• 1,280 Kbit dual-port SRAM with variable data width divided in 32 SRAM blocks
• Dual ported Block RAMs with 20-80 bit data width, also configurable as FIFO
• Multipliers with arbitrary factor width implementable
• Multiple clocking schemas
• All GPIOs configurable as single-ended or LVDS differential type and support double data rate (DDR)

Package

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• FPGA in ball grid package for low size and high pin count
• Only 2 signal layers required on PCB

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Here you can find all relevant documentation for GateMate^TM FPGA. Files are gouped by topic, so you will have quick access to the requested information. Please feel free to contact us for any questions.

Note: Data can change without notice. Parts of the information presented may be protected by patent or other rights.

GateMate^TM Evaluation Board
Start directly with your application development! The GateMate^TM Evaluation Board is a feature-rich, ready-to-use development platform for the CCGM1A1.

It serves as a reference design and for a direct entry into application development. User applications can be tailored to each of the nine available I/O banks. Attaching additional hardware is a breeze thanks to the Pmod connectors: They allow access to a variety of peripheral boards, including motor controllers, sensors, displays and more.

Interfaces

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• Nine sophisticated I/O banks
• Two standard 12-pin Pmod connectors
• One high-speed 2.5 Gb/s SerDes connector
• Access to all four clock inputs
• Configuration via JTAG, flash or on-board SPI programmer

Memory

• 32 Mbit quad SPI flash
• 512 Mbit DDR-SDRAM

Power

• User-selectable core and I/O voltages
• Powered from 5V USB

GateMate^TM FPGA Series: Feature Summary by Device

The Cologne Chip GateMate^TM family addresses a complete range of system requirements. The following table compares all available devices:

1) CPEs have 2x4 or 8 inputs connected to a LUT tree 2) Each CPE can be used as 2x2 Multiplier tile 3) Block RAM can have a max data width of 20 either 40 Bits